The threshold voltage Vth of a field-effect transistor (FET) is the minimal value of gate-source voltage for which a current can flow via a conducting channel connecting the transistor's source and drain terminals. While for wide planar transistors the threshold voltage is a well-defined characteristic substantially independent of the drain-source voltage, in modern ultra-scale FETs, e.g. nanometer-sized metal-oxide semiconductor field-effect transistors (MOSFET), the threshold voltage is not as stable, for example due to drain-induced barrier lowering.
In ultra-scaled devices, such as high-end memory modules, system-on-chip (SoC) devices or field-programmable gate arrays (FPGA), the OFF-state current IOFF may typically increase with the thinning of the gate oxide dielectric Tox and the reduction of the gate length Lgate. In fact, both Drain Induced Barrier Lowering (DIBL) and Gate Induced Drain Leakage (GIDL) may cause the electric field in the channel between the Source and Drain to increase. The electrons flowing into the nMOS may thus be accelerated by a stronger lateral electric field, which induces higher impact ionization and may cause related reliability problems.
In a standard complementary metal-oxide semiconductor (CMOS) inverter, the N-channel MOSFET transistor is stressed in different ways during its operating life. When the device is in the ON-state, e.g. gate and drain voltages tied to the supply voltage: Vg=Vd=Vdd, it is subject to hot carrier injection (HCl), e.g. channel hot electron (CHE) injection. When the device is biased with a high drain voltage Vd while the gate voltage Vg=0 V, and source and body are polarized at ground, OFF-State Stress (OSS) can occur. This Off-State Stress, also known as Non Conductive Stress (NCS), is a degradation phenomenon occurring in both NMOS and PMOS. While HCl degradation occurring in the ON-state is an extensively studied phenomenon, the OSS degradation occurring in the OFF-state has received little attention in the past, since it may have been considered to convey less risk than degradation in the ON-state.
The OSS degradation phenomenon has been studied for poly-SiO2 technology, but although the OSS effect was measurable, it was found not to represent a significant source of degradation, e.g. the threshold voltage Vth shift induced by nMOS OFF-State Stress degradation may be substantially smaller than the Vth shift induced by pMOS negative-bias temperature instability (NBTI). For example, the OSS degradation mechanism and the drain relaxation behaviour of nMOS in advanced technology nodes, down to 65 nm, has been described by Lee et al. in “Effect of OFF-State Stress and Drain Relaxation Voltage on Degradation of a Nanoscale nMOSFET at High Temperature”, IEEE Electron Device Letters 32(7), p. 856.